1. Field of the Invention
The present invention generally relates to computing devices. More specifically, the present invention relates to a processor architecture.
2. Description of the Related Art
Current and future superscalar and very large instruction word (VLIW) processor execution units have highly wire limited implementation caused by the requirement of forwarding results from multiple execution units to each other at frequencies above 10 GHz and the fact of, in 65 nm or less lithography in CMOS technologies, bus wiring scales very poorly.
This lack of scaling is very much exacerbated by high-frequency skin effects in conductors that limit conductivity to only surfaces of wires. Generally, the data path wiring must be overscaled so that their size is limited. However, the FET devices themselves are very small, especially n devices that form the great preponderance of gates in high-speed dynamic designs such as adders, rotators, and register files. Thus, wiring limited designs, where FET devices are little more than half of the total area, are apparently wasteful of chips space in the absence of real implementations. These designs are, thus, totally wiring limited in both horizontal and vertical dimensions.
Further, each successive CMOS generation more than doubles the power density for functional units as the frequency and density increase with increased pipelining. Today's 130 μm chips already have power densities at or near the practical limits at 2-3 GHz. Thus, it is virtually impossible to make run time functional use of the unused devices under wire limited functional units.